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PMC
FEATURES
* Single Power Supply Operation - 5.0 V 10% Read/Program/Erase * High Performance Read - 55/70/90 ns access time * Cost Effective Block Architecture - One 16 Kbytes top or bottom Boot Block with software lockout - Two 8 Kbytes Parameter Blocks - One 96 Kbytes Main Block - One 128 Kbytes Main Block * Automatic Erase and Program - Typical 15 s/byte programming - Typical 40 ms block or chip erase * Hardware Data Protection
ADVANCE INFORMATION
Pm29F002
2 Megabit (256K X 8) 5.0 Volt-only CMOS Flash Memory
* Data# Polling and Toggle Bit Features * Low Power Consumption - Typical 10 mA active read current - Typical 40 mA program/erase current - Typical <0.1 A CMOS standby current * High Product Endurance - Guarantee 10,000 program/erase cycles - Typical 50,000 program/erase cycles - Minimum 10 years data retention * Industrial Standard Pin-out and Packaging - 32-pin Plastic DIP - 32-pin PLCC * Manufactured on 0.30 m process - Fully compatible with previous 0.35 m version
GENERAL DESCRIPTION
The Pm29F002 is a 2 Megabit, 5.0 Volt-only Flash Memory organized as 262,144 bytes of 8 bits each. This device is designed to use a 5.0 Volt power supply to perform in-system programming, 12.0 Volt VPP power supply for program and erase operation is not required. The device can be programmed in standard EPROM programmers as well. The 2 Megabit memory array is divided into five blocks of one 16 Kbytes, two 8 Kbytes, one 96 Kbytes, and one 128 Kbytes for BIOS and parameters storage. The five blocks allow users to flexibly make chip erase or block erase operation flexible. The block erase feature allows a particular block to be erased and reprogrammed without affecting the data in other blocks. After the device performed chip erase or block erase operation, it can be reprogrammed on a byte-by-byte basis. The device has a standard microprocessor interface as well as JEDEC single-power-supply Flash compatible pin-out and command set. The program operation of Pm29F002 is executed by issuing the program command code into command register. The internal control logic automatically handles the programming voltage ramp-up and timing. The erase operation of Pm29F002 is executed by issuing the chip erase or block erase command code into command register. The internal control logic automatically handles the erase voltage ramp-up and timing. The preprogramming on the array which has not been programmed is not required before the erase operation. The device also features Data# Polling and Toggle Bit function, the end of program or erase operation can be detected by Data# Polling of I/O7 or Toggle Bit of I/O6. The device has an optional 16 Kbytes top or bottom boot block with a software lockout feature for data security. The boot block can be used to store user secure code. When the lockout feature is enabled, the boot block is permanently protected from being reprogrammed. The Pm29F002 is manufactured on PMC's 0.30 m advanced nonvolatile technology, P-FLASHTM. The device is packaged in a 32-pin DIP and PLCC with access time of 55, 70 and 90 ns.
Programmable Microelectronics Corp.
1
Issue Date: March, 2001 Rev:1.0
PMC
CONNECTION DIAGRAMS
Pm29F002
WE# 31
A12
A15
A16
V CC
NC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
V CC WE# A17 A14 A13 A8 A9 A11 OE# A10 CE# I/O7 I/O6 I/O5 I/O4 I/O3
A7 A6 A5 A4 A3 A2 A1 A0 I/O0
5 6 7 8 9 10 11 12 13 14 I/O1
4
3
2
NC
1
32
30
A17 29 28 27 26 25 24 23 22 21
A14 A13 A8 A9 A11 OE# A10 CE# I/O7
15 I/O2
16 GND
17 I/O3
18 I/O4
19 I/O5
20 I/O6
32-Pin PDIP
32-Pin PLCC
LOGIC SYMBOL
18 A0-A17 8 I/O0-I/O7 CE# OE# WE#
Programmable Microelectronics Corp.
2
Issue Date: March, 2001 Rev: 1.0
PMC
PRODUCT ORDERING INFORMATION
Pm29F002 T -55 PC Temperature Range C = Commercial (0C to +70C)
Pm29F002
Package Type P = 32-pin Plastic DIP (32P) J = 32-pin Plastic J-Leaded Chip Carrier (32J) Speed Option Boot Block Location T = Top Boot Block B = Bottom Boot Block PMC Device Number
Part Number Pm29F002T-55JC
tACC
(ns)
B oot Location Top
P ackag e 32J 32P
Temperature R an g e
Pm29F002T-55PC 55 Pm29F002B-55JC Bottom PM29F002B-55PC Pm29F002T-70JC Pm29F002T-70PC 70 Pm29F002B-70JC Pm29F002B-70PC Pm29F002T-90JC Pm29F002T-90PC 90 Pm29F002B-90JC Pm29F002B-90PC Bottom Top Bottom Top
32J 32P 32J 32P 32J 32P 32J 32P 32J 32P
Commercial (0C to +70C)
Commercial (0C to +70C)
Commercial (0C to +70C)
Note: Valid combination list for the Pm29F002. Please consult the local PMC sales office, sales representatives or distributors to confirm the availability of specific valid combination and delivery schedule.
Programmable Microelectronics Corp.
3
Issue Date: March, 2001 Rev: 1.0
PMC
PIN DESCRIPTIONS
Pm29F002
SYMBOL A 0 - A 17
TYPE INPUT
DESCRIPTION Address Inputs: For memory addresses and command register. Addresses are internally latched during a write cycle. Chip Enable: CE# low activates the device's internal circuitries for device operation. CE# high deselects the device and switches into standby mode to reduce the power consumption. Please refer to DC characteristics table. Write Enable: Activate the device for write operation. WE# is active low. Output Enable: Control the device's data buffers during a read cycle. OE# is active low. Data Inputs/Outputs: Inputs array data during program operation, when CE# and WE# are active. Data is internally latched during the write and program cycles. When CE# and OE# are active, the output sends array data, manufacturer code or device code. The data pins float to tri-state when the chip is deselected or the outputs are disabled. Device Power Supply Ground No Connection
C E#
INPUT
WE# OE#
INPUT INPUT
I/O0 - I/O7
INPUT/ OUTPUT
V CC GND NC
Programmable Microelectronics Corp.
4
Issue Date: March, 2001 Rev: 1.0
PMC
BLOCK DIAGRAM
Pm29F002
ERASE/PROGRAM VOLTAGE GENERATOR
I/O0-I/O7 I/O BUFFERS
HIGH VOLTAGE SWITCH
WE# CE# OE#
COMMAND REGISTER
CE,OE LOGIC
DATA LATCH
SENSE AMP
ADDRESS LATCH
Y-DECODER X-DECODER
Y-GATING MEMORY ARRAY
A0-A17
DEVICE OPERATION
READ OPERATION The access of Pm29F002 is similar as that of EPROM. To obtain data at the outputs, three control functions must be satisfied: * CE# is the chip enable and should be pulled low ( VIL ). * OE# is the output enable and should be pulled low ( VIL). * WE# is the write enable and should remains high ( VIH ). BOOT BLOCK LOCKOUT The device has a software lockout feature to prevent the data in the boot block from being erased or reprogrammed. The boot block can be located at the top or bottom of the address location. The block size is 16 Kbytes. Once the lockout feature is enable, the boot block can not be erased or reprogrammed. Data in the main memory block can still be updated through the regular programming method. The boot block lockout feature can be turned on by issuing a six-bus-cycle command sequence. Please refer to Table 4 and Chart 4.
Programmable Microelectronics Corp.
BOOT BLOCK LOCKOUT DETECTION The state of the Boot Block lockout can be detected by software product identification entry. After entry, selects Boot Block address with A0 = "0" and A1 = "1" and then read I/O0. A data of "0" means the lockout feature is disabled and the Boot Block can be erased or programmed. A data of "1" means the lockout feature is enabled and the Boot Block is protected. Product identification exit must be executed before the device returns to read mode. PRODUCT IDENTIFICATION The product identification mode can be used to identify the device and the manufacturer by hardware or software operation. The hardware operation mode is activated by applying a 12.0 Volt on A9 pin, typically used by an external programmer to select the right programming algorithm for the device. For detail, please see Bus Operation Modes in Table 3. The software operation mode is activated by three-bus-cycle command. Please see Software Command Definition in Table 4.
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Issue Date: March, 2001 Rev: 1.0
PMC
DEVICE OPERATION (CONTINUED)
Pm29F002
BYTE PROGRAMMING The programming is a four-bus-cycle operation and the data is programmed into the device (to a logical "0") on a byte-by-byte basis. Please see Software Command Definition in Table 4. A program operation is activated by writing the three-byte command sequence followed by one byte of data into the device. The address are latched on the falling edge of WE# or CE# whichever occurs later, and the data is latched on the rising edge of WE# or CE#, whichever occurs first. The internal control logic automatically handles the internal programming voltages and timing. A data "0" can not be programmed back to a "1". Only erase operation can convert "0"s to "1"s. The Data# Polling of I/O7 or Toggle Bit of I/O6 can be used to detect when the programming operation is completed. CHIP ERASE The entire memory array can be erased through a chip erase operation. Pre-programs the device is not required prior to chip erase operation. Chip erase starts after a six-bus-cycle chip erase command sequence. All commands will be ignored once the chip erase operation has started. The device will return back to read mode after the completion of chip erase. When the boot block lockout feature is enabled, the boot block will not be erased during a chip erase operation. Only the parameter blocks and the main blocks will be erased. BLOCK ERASE The memory array is organized into five blocks: one 16 Kbytes boot block, two 8 Kbytes parameter blocks, one 96 Kbytes and one 128 Kbytes main blocks. A block erase operation allows to erase any individual block. Pre-programs the block is not required prior to block erase operation. If the boot block lockout feature is enable, the block erase command attempts to erase the boot block will be ignored. The block erase command is similar to chip erase command except for the last bus cycle command where the block addresses are used to select the block for erasure and the input data to the I/Os is 30h. Each block erase operation erases one block. Block erase and chip erase are both internally controlled and timed.
I/O7 DATA# POLLING The Pm29F002 provides Data# Polling feature to indicate the process or the completion of a program or erase cycle. During a program cycle, an attempt to read the device will result in the complement of the last loaded data on I/O7. Once the program cycle is completed, the true data of the last loaded data is valid on all outputs. During a block or chip erase operation, an attempt to read the device will result a "0" on I/O7. After the erase cycle is completed, an attempt to read the device will result a "1" on I/O7. I/O6 TOGGLE BIT The Pm29F002 also provides Toggle Bit feature as a method to detect the process or the end of a program or erase cycle. During a program or erase operation, an attempt to read data from the device will result in I/O6 toggling between "1" and "0". When the program or erase operation is complete, I/O6 will stop toggling and valid data will be read. Toggle bit may be accessed at any time during a program or erase cycle. HARDWARE DATA PROTECTION Hardware data protection protects the device from unintentional erase or program operation. It is performed in the following ways: (a) VCC sense: if VCC is below 3.8 V (typical), the program function is inhibited. (b) Write inhibit: holding any of the signal OE# low, CE# high or WE# high inhibits a write cycle. (c) Noise filter: pulses of less than 20 ns (typical) on the WE# or CE# inputs will not initiate a write cycle.
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
MEMORY BLOCKS AND ADDRESSES
Table 1. Top Boot Block Address Table (Pm29F002T)
Block Main Block 2 Main Block 1 Parameter Block 2 Parameter Block 1 Boot Block Block Siz e 128 Kbytes 96 Kbytes 8 Kbytes 8 Kbytes 16 Kbytes
Pm29F002
Address Range 00000h-1FFFFh 20000h-37FFFh 38000h-39FFFh 3A000h-3BFFFh 3C000h-3FFFFh
Table 2. Bottom Boot Block Address Table ( Pm29F002B)
Block Boot Block Parameter Block 1 Parameter Block 2 Main Block 1 Main Block 2 Block Siz e 16 Kbytes 8 Kbytes 8 Kbytes 96 Kbytes 128 Kbytes Address Range 00000h-03FFFh 04000h-05FFFh 06000h-07FFFh 08000h-1FFFFh 20000h-3FFFFh
OPERATING MODES
Table 3. Bus Operation Modes
Mode Read Write Standby Output Disable
C E# VIL VIL VIH X
OE# VIL VIH X VIH
WE# VIH VIL X X
ADDRESS X
(1)
I/O DOUT DIN High Z High Z Manufacturer Code Device Code
(3) (3)
X X X A2 - A17 = X, A9 = VH (2), A1 = VIL, A0 = VIL A2 - A17 = X, A9 = VH (2), A1 = VIL, A0 = VIH
Product Identification Hardware
VIL
VIL
VIH
Notes: 1. X can be VIL, VIH or addresses. 2. VH = 12.0 V 0.5 V.
Programmable Microelectronics Corp.
3. Manufacturer Code: 9Dh; Device Code: 1Dh (top boot), 2Dh (bottom boot) 7
Issue Date: March, 2001 Rev: 1.0
PMC
COMMAND DEFINITION
Table 4. Software Command Definition
Pm29F002
Command S eq u en ce Read Chip Erase Block Erase Byte Program Boot Block Lockout (2,3) Boot Block Lockout Detection (3) Product Manufacturer ID Product Device ID (Top Boot) Product Device ID (Bottom Boot) Product ID Exit (6) Product ID Exit (6)
B us Cycle 1 6 6 4 6
1st B u s Cycle Addr Data Addr DOUT 555h A A h 555h A A h 555h A A h 555h A A h
2n d B u s Cycle Addr Data
3rd Bus Cycle Addr Data
4th Bus Cycle Addr Data
5th Bus Cylce Addr Data
6th Bus Cycle Addr Data
2A A h 55h 2A A h 55h 2A A h 55h 2A A h 55h
555h 80h 555h 80h 555h A 0h 555h 80h
555h A A h 555h A A h Addr DIN 555h A A h BA
(4) (4)
2A A h 55h 2A A h 55h
555h 10h BA (1) 30h
2A A h 55h
555h 40h
00h (5) 01h (5)
3
555h A A h
2A A h 55h
555h 90h BA
3 3 3 3 1
555h A A h 555h A A h 555h A A h 555h A A h X X X h F 0h
2A A h 55h 2A A h 55h 2A A h 55h 2A A h 55h
555h 90h 555h 90h 555h 90h 555h F 0h
X 00h 9D h X 01h 1D h X 01h 2D h
Notes: 1. BA = Block address of the block to be erased. 2. When the boot block lockout feature is enabled, the boot block will not be erased when a chip erase command or a block erase command for boot block erasure is issued. Once the boot block is not protected, the boot block will be erased when a chip erase command or a block erase command for boot block erasure is issued. 3. After completion of the boot block lockout enable or detection command, the Product ID Exit command must be issued to return to standard read mode. 4. BA = Block address of the boot block; For top boot block location, A0 = "0", A1 = "1", and A14-A17 = "1" where A2-A13 = Don't Care; For bottom boot block location, A0 = "0", A1 = "1", and A14-A17 = "0" where A2-A13 = Don't Care. 5. I/O0 = "1" means boot block lockout is enabled, I/O0 = "0" means boot block lockout is disabled. 6. Either one of the Product ID Exit command can be used.
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
DEVICE OPERATIONS FLOWCHARTS
AUTOMATIC PROGRAMMING
Pm29F002
Start
Load Data AAh to Address 555H
Load Data 55h to Address 2AAh
Address Increment
Load Data A0h to Address 555h
Load Program Data to Program Address
I/O7 = Data? or I/O6 Stop Toggle?
No
Yes
Last Address? No Yes Programming Completed
Chart 1. Automatic Programming Flowchart
Programmable Microelectronics Corp.
9
Issue Date: March, 2001 Rev: 1.0
PMC
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
AUTOMATIC ERASE
Start
Pm29F002
Write Chip or Block Erase Command
No
Data = FFh? or I/O6 Stop Toggle? Yes Erasure Completed
CHIP ERASE COMMAND
Load Data AAh to Address 555h
BLOCK ERASE COMMAND
Load Data AAh to Address 555h
Load Data 55h to Address 2AAh
Load Data 55h to Address 2AAh
Load Data 80h to Address 555h
Load Data 80h to Address 555h
Load Data AAh to Address 555h
Load Data AAh to Address 555h
Notes: 1. Please see Software Command Definition in Table 1 and Table 2 for block addresses. 2. Only erase one block per each block erase cycle. 3. When the boot block lockout feature has been enabled, the boot block will not be erased.
Load Data 55h to Address 2AAh
Load Data 55h to Address 2AAh
Load Data 10h to Address 555h (3)
Load Data 30h to Block Address (1,2,3)
Chart 2. Automatic Erase Flowchart
Programmable Microelectronics Corp.
10
Issue Date: March, 2001 Rev: 1.0
PMC
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
SOFTWARE PRODUCT IDENTIFICATION ENTRY
Pm29F002
SOFTWARE PRODUCT IDENTIFICATION EXIT
Load Data AAh to Address 555h
Load Data AAh to Address 555h
Load Data 55h to Address 2AAh
Load Data 55h to Address 2AAh or
Load Data F0h to Address XXXh
Load Data 90h to Address 555h
Load Data F0h to Address 555h
Exit Product Identification Mode (3)
Enter Product Identification Mode (1,2)
Exit Product Identification Mode (3)
Notes: 1. Manufacturer Code is read when A0-A17 = XX00h, where X = Don't Care; Device Code is read when A0-A17 = XX01h. 2. Manufacturer Code = 9Dh; Device Code = 1Dh (top boot device); Device Code = 2Dh (bottom boot device). 3. The device returns to standard read operation.
Chart 3. Software Product Identification Entry/Exit Flowchart
Programmable Microelectronics Corp.
11
Issue Date: March, 2001 Rev: 1.0
PMC
DEVICE OPERATIONS FLOWCHARTS (CONTINUED)
BOOT BLOCK LOCKOUT ENABLE (1,2)
Load Data AAh to Address 555h
Pm29F002
Load Data 55h to Address 2AAh
Load Data 80h to Address 555h
Load Data AAh to Address 555h
Notes: 1. Please call manufacturer for the command code to disable the boot block lockout. 2. After excuting the boot block lockout command, the Product ID Exit command must be issued to return to standard read mode.
Load Data 55h to Address 2AAh
Load Data 40h to Address 555h
Pause 500 ms
Boot Block Lockout Enabled
Chart 4. Boot Block Lockout Enable Flowchart
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
ABSOLUTE MAXIMUM RATINGS (1)
Pm29F002
Temperature Under Bias Storage Temperature Input Voltage with Respect to Ground on All Pins except A9 pin (2) Input Voltage with Respect to Ground on A9 pin (3) All Output Voltage with Respect to Ground VCC (2)
-65OC to +125OC -65OC to +125OC -0.5 V to +6.25 V -0.5 V to +13.0 V -0.5 V to VCC + 0.6 V -0.5 V to +6.25 V
Notes: 1. Stresses under those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. The functional operation of the device or any other conditions under those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating condition for extended periods may affected device reliability. 2. Maximum DC voltage on input or I/O pins are +6.25 V. During voltage transitioning period, input or I/O pins may overshoot to VCC + 2.0 V for a period of time up to 20 ns. Minimum DC voltage on input or I/O pins are -0.5 V. During voltage transitioning period, input or I/O pins may undershoot GND to -2.0 V for a period of time up to 20 ns. 3. Maximum DC voltage on A9 pin is +13.0 V. During voltage transitioning period, A9 pin may overshoot to +14.0 V for a period of time up to 20 ns. Minimum DC voltage on A9 pin is -0.5 V. During voltage transitioning period, A9 pin may undershoot GND to -2.0 V for a period of time up to 20 ns.
DC AND AC OPERATING RANGE
Part Number Operating Temperature Vcc Power Supply Pm29F002 0oC to 70oC 4.5 V - 5.5 V
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
DC CHARACTERISTICS
Pm29F002
Symbol ILI ILO ISB1 ISB2 ICC1 ICC2 (1) VIL VIH VOL VOH
Parameter Input Load Current Output Leakage Current VCC Standby Current CMOS VCC Standby Current TTL VCC Active Read Current VCC Program/Erase Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage
Condition VIN = 0 V to VCC, VCC = VCC max VI/O = 0 V to VCC, VCC = VCC max CE#, OE# = VCC 0.5 V CE# = VIH to VCC f = 5 MHz; IOUT = 0 mA
Min
Typ
Max 1 1
Units A A A mA mA mA V V V V
0.1 0.2 10 40 -0.5 2.0
5 3 30 60 0.8 VCC + 0.5 0.45
IOL = 5.8 mA, VCC = VCC min IOH = -400 A, VCC = VCC min 2.4
Note: 1. Characterized but not 100% tested.
AC CHARACTERISTICS
READ OPERATIONS CHARACTERISTICS
Pm29F002-55 Parameter Min Read Cycle Time Address to Output Delay CE# to Output Delay OE# to Output Delay CE# or OE# to Output High Z Output Hold from OE#, CE# or Address, whichever occured first VCC Set-up Time 0 0 50 55 55 55 30 20 0 0 50 Max Min 70 70 70 35 25 0 0 50 Max Min 90 90 90 40 30 Max ns ns ns ns ns ns s Pm29F002-70 Pm29F002-90 Units
Symbol tRC tACC tCE tOE tDF tOH tVCS
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
AC CHARACTERISTICS (CONTINUED)
READ OPERATIONS AC WAVEFORMS
tR C
ADDRESS ADDRESS VALID
Pm29F002
CE#
tA C C tC E tO E tD F
OE#
WE#
tO H
OUTPUT HIGH Z
OUTPUT VALID
tV C S
V CC
OUTPUT TEST LOAD
5.0 V
INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL
1.8 K OUTPUT PIN
3.0 V Input 0.0 V 1.5 V
AC Measurement Level
1.3 K
100 pF
PIN CAPACITANCE ( f = 1 MHz, T = 25C )
Typ CIN COUT 4 8 Max 6 12 Units pF pF Conditions VIN = 0 V VOUT = 0 V
Note: These parameters are characterized and are not 100% tested.
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
AC CHARACTERISTICS (CONTINUED)
WRITE (PROGRAM/ERASE) OPERATIONS CHARACTERISTICS
Pm29F002-55 Symbol tWC tAS tAH tCS tCH tWS tWH tDS tDH tWP tWPH tBP tEC tVCS Parameter Min Wri te C ycle Ti me Address Set-up Ti me Address Hold Ti me C E# Set-up Ti me C E# Hold Ti me WE# Set-up Ti me WE# Hold Ti me D ata Set-up Ti me D ata Hold Ti me Wri te Pulse Wi dth Wri te Pulse Wi dth Hi gh Byte Programmi ng Ti me C hi p or Block Erase C ycle Ti me VCC Set-up Ti me 50 55 0 45 0 0 0 0 30 0 35 20 50 100 50 Max Min 70 0 45 0 0 0 0 30 0 35 20 50 100 50 Max Min 90 0 50 0 0 0 0 45 0 45 20 Pm29F002-70
Pm29F002
Pm29F002-90 U nits Max ns ns ns ns ns ns ns ns ns ns ns 50 100 s ms s
PROGRAM OPERATIONS AC WAVEFORMS - WE# CONTROLLED
Program Cycle OE#
tV C S
CE#
tC H
tC S
WE#
tW P
tW P H
tB P
tA S
A0 - A17
tA H
555 2AA 555 ADDRESS
tW C tD S
DATA IN AA 55
tD H
A0
INPUT DATA VALID DATA
V CC
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
AC CHARACTERISTICS (CONTINUED)
PROGRAM OPERATIONS AC WAVEFORMS - CE# CONTROLLED
Program Cycle OE#
Pm29F002
tV C S
WE#
tW H
tW S
CE#
tW P
tW P H
tB P
tA S
A0 - A17
tA H
555 2AA 555 ADDRESS
tW C tD S
DATA IN AA 55
tD H
A0
INPUT DATA VALID DATA
V CC
CHIP ERASE OPERATIONS AC WAVEFORMS
OE#
tV C S
CE#
tW P
WE#
tW P H tD H
tA S
AO - A17
tA H
555 tW C AA 2AA
555
555
2AA
555
tD S
55 80 AA 55 10
tE C
DATA IN
V CC
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
AC CHARACTERISTICS (CONTINUED)
BLOCK ERASE OPERATIONS AC WAVEFORMS
Pm29F002
OE#
tV C S
CE#
tW P
WE#
tW P H tD H
tA S
AO - A17
tA H
555 tW C AA 2AA
555
555
2AA
BLOCK ADDRESS
tD S
55 80 AA 55 30
tE C
DATA IN
V CC
PROGRAM/ERASE PERFORMANCE
Parameter Block Erase Time Chip Erase Time Byte Programming Time Program/Erase Endurance
Unit ms ms s Cycles
Min
Typ 40 40 15
Max 100 100 50
Remarks From writing erase command to erase completion From writing erase command to erase completion Excludes the time of four-cycle program command execution
10,000
50,000
Note: These parameters are characterized and are not 100% tested.
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
AC CHARACTERISTICS (CONTINUED)
TOGGLE BIT AC WAVEFORMS
Pm29F002
WE#
tO E H
CE#
OE#
tO E
I/O6
DATA TOGGLE TOGGLE STOP TOGGLING
tD F tO H
VALID DATA
Note:
Toggling either CE#, OE# or both OE# and CE# will operate Toggle Bit.
DATA# POLLING AC WAVEFORMS
WE# CE#
tC H
tC E tO E H
OE#
tO E
I/O7 I/O7# VALID DATA
tD F
tO H
Note:
Toggling either CE#, OE# or both OE# and CE# will operate Data# Polling.
Programmable Microelectronics Corp.
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Issue Date: March, 2001 Rev: 1.0
PMC
PACKAGE TYPE INFORMATION 32P
32-Pin Plastic DIP Dimensions in Inches (Millimeters)
1.640(41.7) 1.680(42.7) 32 17 .537(13.64) .557(14.05) Pin 1 I.D. 16 .005(.127) MIN
0 10 .625(15.88) .665(16.89)
Pm29F002
.600(15.24) .625(15.88)
.008(0.20) .013(0.33)
.040(1.02) .065(1.65)
.146(3.71) .162(4.11)
SEATING PLANE .120(3.05) .160(4.07) .090(2.29) .110(2.79) .014(.36) .022(.56)
.015(.38) MIN
32J
32-Pin Plastic Leaded Chip Carrier Dimensions in Inches (Millimeters)
.485(12.32) .495(12.51)
.447(11.35) .453(11.51)
.009 .015 025(.635)X30
.585(14.86) .595(15.11) Pin 1 I.D. .547(13.89) .553(14.05)
.123(3.12) .140(3.56) .076(1.93) .095(2.41)
SEATING PLANE
.400 REF. .510(12.95) .530(13.46) .013(.33) .021(.53)
.026(.66) .032(.81)
.050 REF.
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Programmable Microelectronics Corp.
20
Issue Date: March, 2001 Rev: 1.0
PMC
REVISION HISTORY
Pm29F002
Date March, 2001
Revision No. 1.0
Description of Changes New publication
P ag e N o . All
Programmable Microelectronics Corp.
21
Issue Date: March, 2001 Rev: 1.0

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